1. Field of the Invention
The present invention relates generally to semiconductor signal translators.
2. Description of the Related Art
A variety of semiconductor families are available for forming modern electronic circuits. Each have advantages and disadvantages and typically require different operating signals. For example, bipolar circuits that are arranged in emitter-coupled structures (termed ECL when used for emitter-coupled logic applications) are fast and generate currents that can drive capacitive loads. This same current generation, however, causes them to consume significant power. In contrast, metal-oxide semiconductor (CMOS) circuits use significantly less power and, although they are generally slower than equivalent bipolar circuits, their low power dissipation makes them particularly suited for realizing densely-packed logic circuits.
When used with a rail-to-rail supply voltage of five volts, for example, guaranteed high and low CMOS logic levels are typically narrow windows (e.g., one-half volt) that adjoin each supply rail. In contrast, the differential pairs of emitter-coupled bipolar structures operate with a much lower swing (e.g., .about.200 millivolts) between logic levels. In order to realize the advantages of combined bipolar and CMOS circuits, signal translators are therefore required that can convert relatively-low bipolar signal swings to the nearly rail-to-rail signal swings of CMOS circuits.
Various integrated-circuit fabrication technologies have been developed for these semiconductor families. Although many of these processes are exclusively restricted to bipolar fabrication or to CMOS fabrication, BiCMOS technologies also exist that can place both structures on a single integrated-circuit chip. Regardless of the fabrication technology, combined bipolar and CMOS circuits are typically coupled to the same supply rails which adds a further complication to signal transition between them. Nonetheless, various signal translators have been developed for these families (e.g., see U.S. Pat. Nos. 4,794,317; 4,806,799; 4,968,905; 5,075,580; and 5,459,412).
FIG. 1 illustrates an exemplary signal translator 20 that is restricted to bipolar structures so that it is especially suited for realization with bipolar integrated-circuit fabrication technologies. The signal translator 20 has been incorporated in various products (e.g., AD9042 analog-to-digital converters) of Analog Devices, Inc, the assignee of the present invention.
The translator 20 combines complementary first and second differential pairs 22, active loads in the form of current mirrors 24 and 25 and an output stage 26 that has complementary transistors 28 and 29. In response to typical bipolar signal levels at an input port 32, the complementary differential pairs 22 steers currents I.sub.1 to and away from transistors 34 and 35 of the current mirrors. In response to these steered currents, the transistors 28 and 29 communicate output signals via their coupled collectors at a single-ended output port 36.
Because the complementary transistors 28 and 29 are arranged in common-emitter configurations, their coupled collectors can deliver signals that are very near the +V and -V supply rails 38 and 39. In addition, transistors 28 and 29 can generate the currents necessary to drive capacitive loads such as those formed by CMOS circuits and their associated parasitic integrated-circuit capacitances. When driving capacitive loads, an initially high current from transistor 28, for example, will exponentially fall to a small sustaining trickle current as the voltage at the output port 36 approaches the supply rail 38.
The signal at the output port 36 is thus suitable for driving CMOS circuits. Without additional circuitry, however, transistors 28, 29, 34 and 35 will saturate which degrades the speed of the signal translator 20. Accordingly, voltage clamps 42 and 43 are connected to the collectors of transistors 34 and 35. Resistors 44 and 45 respectively couple transistors 48 and 49 of the complementary differential pairs 22 to current-mirror transistors 34 and 35 and diodes 50 and 51 respectively couple the same differential pairs transistors to the output port 36. Finally, current sources 52 and 53 generate currents I.sub.2 and are connected between emitters and bases of respective output transistors 28 and 29.
In operation of the translator 20, it is intended that each of the transistors 34 and 35 is on when its associated output transistor is off. The clamps 42 and 43 can be realized in various ways to limit the voltage between the collectors of transistors 34 and 35 and their respective supply rails to a value (e.g., .about.300 millivolts) that is sufficient to prevent their saturation while insuring that their associated output transistors 28 and 29 are off.
When a current I.sub.1 is steered through transistor 48, it initially flows through resistor 44 and turns on output transistor 28. In response, the single-ended signal at the output port 36 rises to a potential at which it turns on diode 50. Ignoring the small base current of output transistor 28 and the small trickle current flowing to the output port 36 and given that I.sub.1 &gt;I.sub.2, it is apparent that the circuit stabilizes with current I.sub.2 flowing through resistor 44 and a current I.sub.1 -I.sub.2 flowing from output transistor 28 to differential-pair transistor 48 through diode 50.
Because the voltage drop V.sub.d across diode 50 substantially matches the base-emitter drop V.sub.be of the output transistor 28, the collector potential of transistor 28 is limited below the supply rail 38 by the product of the current I.sub.2 and the resistance of resistor 44. For a given value of the current I.sub.2, an appropriate resistance of the resistor 44 can thus be chosen to limit the voltage between the output port 36 and the supply rail 38 to a value (e.g., .about.300 millivolts) that is sufficient to prevent saturation of the output transistor 28. The operation described above is repeated in complementary fashion for output transistor 29 when the input signal at the input port 32 causes current to be steered through transistor 49.
It has been observed however, that the speed of the translator 20 is degraded because when each output transistor turns on, it must initially absorb the I.sub.1 current of the other in addition to supplying current for driving a capacitive load. When output transistor 28 turns off, for example, stored charges in its base initially continue to support a current of substantially I.sub.1. As output transistor 29 turns on, it must absorb this current and therefore the current available to drive a capacitive load is initially reduced by I.sub.1 and the time to bring the signal at the output port 36 to a CMOS level is accordingly increased.